This invention relates to a semiconductor memory and, more particularly, to a dynamic random access memory (DRAM) having multiplexed twin I/O line pairs for improved page mode speed performance.
DRAMS are extensively used throughout the computer industry as data storage devices. Their relatively small size, high speed of operation and high storage density render them particularly suitable for the construction of computer memory systems.
In general, a DRAM is comprised of a two dimensional array of binary storage cells organized by rows and columns wherein the presence or absence of a stored charge is indicative of a bit of data. In order to select a desired one of the storage cells for the reading or writing of data therein a plurality of address inputs are provided to the DRAM. To minimize the number of input connections to the DRAM, and hence the package size and cost, the address inputs are typically multiplexed. In operation, the least significant address bits are first applied to their respective address inputs followed by the assertion of a row address strobe (RAS) signal. RAS being asserted causes the row address of the storage array to be latched within the DRAM. The most significant address inputs are next applied followed by the assertion of a column address strobe (CAS) signal. The particular combination of the row and column addresses thus applied is decoded within the DRAM by row address and column address decoder circuitry to select one of the binary storage cells for reading or writing and, also to control the operation of the DRAM.
As may be appreciated, depending on the particular topology of the two dimensional storage array, the number of address inputs and other factors a variety of different decoder circuits may be employed. Illustrative of some of these decoder circuits of the prior art are the following U.S. Patents, namely, two U.S. Pat. Nos. 4,156,938 and 4,477,739 to Proelsting et al, two U.S. Pat. Nos. 4,200,917 and 4,309,629 to Moench, a U.S. Pat. No. 4,309,629 to Kamuro, and a U.S. Pat. No. 4,477,884 to Iwahashi.
Although the foregoing decoder circuits may be suitable for their intended applications, a problem arises when it is desired to perform multiple data accesses to the DRAM in a high speed manner. Referred to as a page mode of operation, this type of access typically requires maintaining RAS in an asserted state to thereby provide a row address to the array. While RAS is so asserted a plurality of column addresses and associated CAS signals are sequentially provided to the DRAM. Thus, a particular row is selected and a plurality of columns within that row are sequentially accessed.
Currently known DRAMS have one I/O line pair, or bus, for connecting the outputs of a plurality of storage array sense amplifiers to an I/O line sense amplifier during the time that CAS is asserted. The use of one I/O line pair requires that some minimum interval of time be allowed between successive assertions of CAS in order to allow for the proper precharging of the I/O line pair. Inasmuch as the I/O line sense amplifier is essentially a differential or cross-coupled type of amplifier, such precharging is required to equalize the voltage potential between the two lines of the I/O line pair, thus ensuring the proper operation of the sense amplifier for sensing the state of a data bit appearing on the I/O line pair. This requirement of precharging the single I/O line pair between successive assertions of CAS results in a limitation of the number of bits which may be read from or stored within the DRAM during a given interval of time.